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description
- Clock Management: PLL
- Core Supply Voltage Max: 5.25V
- Core Supply Voltage Min: 4.75V
- FPGA Family: 40MX Family
- I/O Supply Voltage: 5V
- Logic Case Style: PLCC
- MSL: MSL 3 - 168 hours
- No. of I/O's: 34I/O's
- No. of Logic Blocks: 295
- No. of Macrocells: -
- No. of Pins: 44Pins
- No. of Speed Grades: -
- Operating Frequency Max: 139MHz
- Product Range: A40MX Series
- Total RAM Bits: -